I’m beginning to think that the Windows PC that I built in 2015 is ready for retirement (though if Joe Biden can be president at 78, maybe this PC can last until 2029?). In looking at new des…

Why aren’t motherboards mostly USB-C by now?::I’m beginning to think that the Windows PC that I built in 2015 is ready for retirement (though if Joe Biden can be president at 78, maybe this PC can last until 2029?). In looking at new des…

  • MHLoppy@fedia.io
    2·
    1 year ago

    Isn’t this glossing over that (when allocating 16 PCIe lanes to a GPU as per your example), most of the remaining I/O connectivity comes from the chipset, not directly from the CPU itself?

    There’ll still be bandwidth limitations, of course, as you’ll only be able to max out the bandwidth of the link (which in this case is 4x PCIe 4.0 lanes), but this implies that it’s not only okay but normal to implement designs that don’t support maximum theoretical bandwidth being used by all available ports and so we don’t need to allocate PCIe lanes <-> USB ports as stringently as your example calculations require.

    Note to other readers (I assume OP already knows): PCIe lane bandwidth doubles/halves when going up/down one generation respectively. So 4x PCIe 4.0 lanes are equivalent in maximum bandwidth to 2x PCIe 5.0 lanes, or 8x PCIe 3.0 lanes.

    edit: clarified what I meant about the 16 “GPU-assigned” lanes.

    • apt_install_coffee@lemmy.mlEnglish
      5·
      1 year ago

      Typically no, the top two PCIE x16 slots are normally directly to the CPU, though when both are plugged in they will drop down to both being x8 connectivity.

      Any PCIE x4 or X1 are off the chipset, as well as some IO, and any third or fourth x16 slots.

      So yes, motherboards typically do implement more IO connectivity than can be used simultaneously, though they will try to avoid disabling USB ports or dropping their speed since regular customers will not understand why.

      • MHLoppy@fedia.io
        3·
        1 year ago

        Typically no, the top two PCIE x16 slots are normally directly to the CPU, though when both are plugged in they will drop down to both being x8 connectivity.

        Any PCIE x4 or X1 are off the chipset, as well as some IO, and any third or fourth x16 slots.

        I think the relevant part of my original comment might’ve been misunderstood – I’ll edit to clarify that but I’m already aware that the 16 “GPU-assigned” lanes are coming directly from the CPU (including when doing 2x8, if the board is designed in this way – the GPU-assigned lanes aren’t what I’m getting at here).

        So yes, motherboards typically do implement more IO connectivity than can be used simultaneously, though they will try to avoid disabling USB ports or dropping their speed since regular customers will not understand why.

        This doesn’t really address what I was getting at though. The OP’s point was basically “the reason there isn’t more USB is because there’s not enough bandwidth - here are the numbers”. The missing bandwidth they’re mentioning is correct, but the reality is that we already design boards with more ports than bandwidth - hence why it doesn’t seem like a great answer despite being a helpful addition to the discussion.